MC4046 Frequency/Phase Detector Offset

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MC4046 Frequency/Phase Detector Offset

The Motorola 4046 Phase-Locked Loop uses a Frequency/Phase detector for the PC2 output. The data sheet indicates the output goes to a high-impedance state when the reference and VCO signals are in phase.

A SPICE analysis shows that both output transistors are turned on briefly each cycle before going to the high-impedance state.

When both transistors are on, the output voltage depends on the match between them. Since this voltage will probably be different from the DC operating point of the loop, the loop will have to create a phase offset between the REF and VCO signals to correct the error.

The phase offset error is proportional to the duty cycle and increases with frequency. It is sensitive to temperature, supply voltage, and variations from one device to the next.

The logic diagram for the PC2 phase detector from the 74HC4046 data sheet (Figure 6, Page 8) is shown below.

Fig. 1. Portion of Motorola 74HC4046 data sheet (Figure 6, Page 8)

The circuit was entered into MicroCap V for analysis. A RESET input was added to initialize the phase detector. NoAlt

Fig. 2. MicroCap Phase Detector SPICE model.

The delay for each gate is the standard TTL default:

.MODEL DLY_TTL UGATE (TPLHTY=11NS TPLHMX=22NS TPHLTY=8NS TPHLMX=15NS)

The Reference input is a 5 MHz square wave:

.DEFINE _REF
+LABEL=START
+0NS 0
+100NS 1
+200NS GOTO START -1 TIMES

The VCO input is a 4.975124... MHz square wave. The first negative transition is 5 ns early, and occurs 1 ns later each cycle:

.DEFINE _VCO
+LABEL=START
+0NS 0
+95NS 1
+195NS 0
+201NS GOTO START -1 TIMES

(The CIR file is available at 4046c.cir)

Figure 3 below shows how the timing relationship changes between the Reference (blue) and VCO (red) signals. The VCO negative transitions start 5 ns early, then occur 1 ns later each cycle:

Fig. 3. VCO signal (red trace) occurs later each cycle.

Figure 4 extends the plot to 10 us to show samples that are early, on time, and late. The UP and DN signals occur each cycle:

Fig. 4. PC2 output for early, on time, and late samples

Results

The simulation shows the UP and DN transistors are turned on briefly each cycle when the loop is in lock.
When both transistors are on, the output voltage depends on the match between them. If this voltage is different from the DC operating point of the loop, it will create a phase offset between the REF and VCO signals. The offset error is proportional to the duty cycle and increases with frequency. It is sensitive to temperature, supply voltage, and variations from one device to the next.

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